A crucial step in design flow is to ensure that the gate-level design representation of an ASIC or system-on-a-chip (SoC) matches the RTL description through formal equivalence checking. Traditionally ...
SAN MATEO, Calif. — In the latest move between the EDA industry's top rivals, Cadence Design Systems Inc. said it has acquired privately held formal verification tool vendor Verplex Inc. for an ...
MILPITAS, Calif.--(BUSINESS WIRE)--Jan. 14, 2002--NEC Corporation today endorsed Conformal(TM) Logic Equivalence Checker (LEC) from Verplex(TM) Systems, Inc., as the formal verification standard for ...
San Jose, Calif., May 13, 2002 - LogicVision, Inc., (NASDAQ:LGVN), a leading provider of embedded test IP for integrated circuits and systems, and Verplex Systems, Inc., provider of high-speed, ...
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