EDN

IMEC Reports Possibility of Sub-45nm CMOS Scaling

At the IEEE International Electron Devices Meeting (IEDM) today, Belgian research center IMEC detailed a simple CMOS integration scheme of a NiSi gate for NMOS and a Ni2Si gate for PMOS on HfSiON with ...
Semiconductor Engineering

Speeding Up NMOS

For years—decades, in fact—the NMOS transistor world has been on cruise control. NMOS is naturally faster and its performance has scaled better than PMOS. PMOS has had a cost advantage. But lately, it ...
Electronic Design

Use Hybrid PMOS-NMOS Active Loads To Cut Substrate Noise In Differential Amplifiers

PMOS transistors are less vulnerable to substrate noise since they’re placed in separate wells; designers implement guard rings to attenuate the substrate noise propagation. However, substrate noise ...
Electronic Design

Dirt Cheap ASIC Design for Dummies (Part 3): NMOS, PMOS Silicon Design Using a Web Browser

Quickly learn what the difference is between PMOS and NMOS transistors in their structure and operation, and how CMOS works with the two in combination. Siliwiz, a free, browser-based, ASIC layout ...
Semiconductor Engineering

Mobility Gets A Boost With Expanded Epi Applications

Even as industry moves into the era of the high k metal gate (HKMG) and FinFET transistor, chipmakers continue to seek ways to improve device performance. One of the latest advances and the subject of ...
Nanowerk

CMOS Technology Explained

Complementary Metal-Oxide-Semiconductor (CMOS) technology is a vital part of modern electronics, used in designing and manufacturing integrated circuits (ICs) that power many digital devices. CMOS ...