EDN

Design verification and debugging FPGA implementations

Verification takes as much as 70% of an ASIC's development time and resources. With growing ASIC complexity, verification problems are growing exponentially. Given the high cost of ASIC mask sets, the ...
Electronic Design

Verification Techniques For FPGA Designs

With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. Timing simulation can be the most revealing verification method; however, it is often ...
EDN

FPGA design and verification using Simulink

Xilinx System Generator for DSP is a MATLAB Simulink block set that facilitates system design. Targeting Xilinx FPGAs within the familiar MATLAB environment, System Generator for DSP gives you the ...
Electronics Weekly

FPGA functional verification: why bother?

FPGA engineers are all doing functional verification using manual processes but growing system comlexity is the issue. Changing tools and methodologies may seem daunting, but there is a way to break ...
Electronics Weekly

FPGA verification for DO-254 is in the hardware

Verifying a complex FPGA design under DO-254 guidelines for use in safety- and mission-critical airborne systems is not without its challenges. Louie De Luna, Aldec Europe’s Product Manager for DO-254 ...
Design-Reuse

Real Intent Introduces Meridian FPGA, Popular Clock Domain Crossing Verification Software for Altera Customers

Sunnyvale, California - November 5, 2008- Real Intent, Inc., the leading supplier of verification software for electronic design, announced its first release of Meridian FPGAâ„¢ verification software.
Business Wire

InterMotion Technology Boosts IP Verification Productivity for Lattice Semiconductor’s CrossLink FPGA Family Using Aldec’s Active-HDL

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, today announced that InterMotion Technology has ...
Electronic Design

Facing Up To Today’s FPGA Verification Challenges

Today it is not unusual for FPGA users to have to deal with more than one language in their designs. At earlier stages of the design development it may be necessary to interface HDL simulation with ...
Semiconductor Engineering

Trends In FPGA Verification Effort And Adoption: The 2018 Wilson Research Group Functional Verification Study

As contributors and pioneers in the digital revolution, we are often so busy creating and innovating that we are compelled to focus on the trees, never mind the forest. But as we are all aware, the ...
Design-Reuse

FPGA Prototyping as a Verification Methodology

To some degree, FPGA prototyping has become commonplace in the majority of SoC development programs. This paper is a brief discussion of four aspects of this type of approach. First the forces behind ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
CIOL

FPGA design verification easier, more economic

SAN JOSE, USA: Real Intent Inc., a leading supplier of verification software for electronic design, announced its first release of Meridian FPGA verification software. Meridian FPGA is specifically ...