EDN

How SystemVerilog aids design and synthesis

The SystemVerilog extensions to Verilog 2001 have been getting a lot of attention lately, especially the new features designed to support verification and testbench design. But SystemVerilog also ...
EDN

An overview of SystemVerilog 3.1

SystemVerilog is an extensive set of enhancements to the IEEE 1364 Verilog-2001 standard. These enhancements provide powerful new capabilities for modeling hardware at the RTL and system level, along ...
Design-Reuse

SystemVerilog key to new design paradigm

SAN JOSE, Calif. — The SystemVerilog 3.1 specification is undergoing final reviews and Synopsys plans to have a synthesis tool for SystemVerilog assertions in the next 12 months, said Synopsys CEO ...
Design-Reuse

Silicon Interfaces announces the release of its Verification Methodology Manual (VMM) based USB 2.0 SystemVerilog Verification IP

CAMPBELL, Calif. -- November 3, 2008--Silicon Interfaces, a high-end design services and leading provider for IPs in Europe, North America and Asia-Pacific, under their IP Development Program - ...
Electronic Design

A Look Back At Verilog

Never in my wildest dreams did I think that the Verilog hardware description language (HDL) would spawn an industry and be a fixture of electronics design for more than 15 years. HDLs were a ...
Electronic Design

What’s the Difference Between VHDL, Verilog, and SystemVerilog?

Designers of electronic hardware describe the behavior and structure of system and circuit designs using hardware description languages (HDLs)—specialized programming languages commonly known as VHDL, ...