Among the many verification challenges confronting system-on-chip designers these days, clock domain crossings (CDCs) rank near the top in difficulty. Two particularly troublesome CDC-related issues ...

As designs move to finFET process nodes, dynamic power reduction has become a requirement. Designers have to eliminate or minimize all sources of redundant switching activity in order to reduce ...

With the increasing complexity of SoC, multiple and independent clocks are essential in the design. Here, Clock Domain Crossings (CDC) are a potential source of design errors. In most of these cases ...